EP93XX. ARM. ®. 9 Embedded Processor Family. EP93xx. User’s Guide 8×8 Key Mtx. ARMT. Maverick. 18 Bit Raster. LCD I/F. Crunch. Notes on making a proper EABI cross compiler for Maverick Crunch (EP, EP93xx) processors. This is a bit of “higher order hacking” and. It’s already configured to build in /opt/toolchains/ directory. This work is based on patches by Martin Guy and tested both on Cirrus demo board for the EP
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Thus, to use it efficiently, integer and floating point instructions must be interleaved so as to keep both processors busy.
Making fast floating point math work on the Cirrus MaverickCrunch floating point unit
Unfortunately these never worked well enough for it to be usable. Most crucially, it fails to take proper account of the way that the FPU sets the condition code registers after a comparison, so the code it generates sometimes gets floating point and bit integer comparisons wrong as well as failing to account for several of the hardware bugs. A branch is taken and it is one of the two instructions in the branch delay slot.
The processor must be operating in serialized mode. The second instruction is not a coprocessor data path instruction.
Toolchain CMP 1 2 3 4 5 6 7 8 9 10 11 12a 12b 13 14 15 Debian gcc 4. In the sample I have tested a TS it is not operating in serialised mode by these criteria because no exceptions are enabled. ArmEabiMaverickCrunch last modified Buggy cfadd – cfaddne – cfstr Buggy cfadd – nop – cfaddne – cfstr Buggy cfadd – cfaddne – nop – cfstr OK cfadd – nop – naverick – cfaddne – cfstr Buggy cfadd – nop maverifk cfaddne – nop – cfstr Buggy cfadd – cfaddne – nop – nop – cfstr OK cfadd – nop – nop – nop – maevrick – cfstr OK cfadd – nop – nop – cfaddne – nop – cfstr OK cfadd – nop – cfaddne – nop – nop – cfstr OK cfadd – cfaddne – nop – nop – nop – cfstr Buggy cfadd – cfaddne – cfaddne – cfstr Buggy cfadd – cfaddne – cfaddne – nop – cfstr OK cfadd – cfaddne – cfaddne – nop – nop – cfstr OK cfadd – eep9302 – cfaddne – cfaddne – macerick OK cfadd – nop – cfaddne – cfaddne – nop – cfstr OK cfadd – nop – cfaddne – cfaddne – nop – nop – cfstr The second instruction may also not be executed because it follows a branch: Skip to main content.
For example, assume no pipeline interlocks other than the dependencies involving register c0 in the following instruction sequence: Views Read Edit View history. GCC doesn’t emit conditional Maverick instructions and the jump case should fixed by mainline’s -mfix-cirrus-invalid-instructions.
Enabling forwarding in a test program on revision E1 hardware, I have been unable to get this bug to bite. Please introduce links to this page from related articles ; try the Find link tool for suggestions. From Wikipedia, the free encyclopedia.
This page was last edited on 19 Aprilat When the error occurs, the result is either coprocessor register or memory corruption.
[linux-cirrus] I’m pretty close with Maverick Crunch on EP – linux-cirrus – FreeLists
Here we only attempt to work around the bugs in the later series. Synchronous mode is much slower, but ensures that, if floating point exceptions are enabled and occur, you can be sure to pinpoint the offending instruction. It fails its condition code check. Characteristics and naming are summarized in the document ZefeerEVB.
Disable interrupts when executing cfldr32 or cfmv64lr instructions. Let the first instruction be a serialized instruction that does not execute. Designers of industrial controls, internet radios, digital media servers, audio jukeboxes, thin clients, set-top boxes, point-of-sale terminals, biometric security systems and GPS devices will benefit from the EP’s integrated architecture and advanced features. It has a -mfix-cirrus-invalid-insns flag, which is supposed to ensure that the two instructions following a branch are not Cirrus one but fails to do so, and that every cfldrdcfldr64cfstrdcfstr64 is followed by one non-Cirrus instruction, which should fix bugs 1 and 2.
Avoid executing these two instructions. The result is that the lower 32 bits of the result stored to memory will be correct, but the upper the 32 bits will be wrong. It has a different instruction set from other floating point accelerators that are found with ARM processors: The sign is unaffected.
When the operand is positive zero, cfnegs and cfnegd write positive zero to the destination register, while the result should be negative zero. Futaris’ strategy includes disabling all conditional instructions other than branch and all bit integer operations. The bugs The bugs are: The result underflows directly to zero. General carrier board design guidelines. Solutions Voice Playback Record Control. Here is how to build a futaris-patched compiler, a summary of their merits, and some benchmarks.
It was removed by GCC 4. When the coprocessor is not in serialized mode and maverock is enabled, memory can be corrupted when two types of instructions appear in the instruction stream with a particular relative timing. The following is from the EP rev E2 errata: The default is non-forwarding. For the latter, Paolo Bonzini [ http: Let the immediately following instruction be a two-word coprocessor load or store.
The EP is a high-performance system-on-chip design that includes a MHz ARM9 processor and is ideal for a range of industrial and consumer electronic applications. Enhance your users’ audio experience through Cirrus Logic’s hardware and software solutions: The kit is composed by: The modifications are published as a megabyte tarball from which a single monolithic patch can be derived by diffing it against the mainline source releases.
The Maverik unit included in the processor core make this modules ideal to run complex and protected operating systems like Linux 2. Mainline GCC support has never worked for it but there is a modified compiler available that does and that is able to generate Crunch-accelerated Debian packages.
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